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NEW QUESTION: 1
What is IP multiplexing on a UNIX host?
A. binding the same IP address to multiple network interface
B. binding more than one MAC address to a single network interface
C. binding more than one IP address to a single network interface
D. increasing throughput on the network interface
Answer: C
NEW QUESTION: 2
Which of the following security controls might force an operator into collusion with personnel assigned organizationally within a different function in order to gain access to unauthorized data?
A. Management monitoring of audit logs
B. Job rotation of operations personnel
C. Enforcing regular password changes
D. Limiting the local access of operations personnel
Answer: D
Explanation:
The questions specifically said: "within a different function" which eliminate
Job Rotation as a choice.
Management monitoring of audit logs is a detective control and it would not prevent collusion.
Changing passwords regularly would not prevent such attack.
This question validates if you understand the concept of separation of duties and least privilege. By having operators that have only the minimum access level they need and only what they need to do their duties within a company, the operations personnel would be force to use collusion to defeat those security mechanism.
Source: TIPTON, Hal, (ISC)2, Introduction to the CISSP Exam presentation.
NEW QUESTION: 3
Which user has the default access to the system shell in clustered Data ONTAP?
A. sysadmin
B. diag
C. admin
D. root
Answer: B
NEW QUESTION: 4
Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?
A. An external DMA engine modifies data in a region of data memory which is already cached by the processor
B. Debugger reads data from a shared, cacheable memory location
C. One core modifies data in a shared cacheable memory region
D. An external agent needs to read data which has been modified by the processor in a cacheable memory region
Answer: D
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