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NEW QUESTION: 1
A. Option D
B. Option A
C. Option B
D. Option C
Answer: C
NEW QUESTION: 2
参加者にDocker for Windowsを紹介するための実践的なワークショップを開発しています。
ワークショップの参加者がデバイスにDockerをインストールできることを確認する必要があります。
出席者がデバイスにインストールする必要がある2つの前提条件コンポーネントはどれですか?それぞれの正解はソリューションの一部を示しています。
注:それぞれの正しい選択には1ポイントの価値があります。
A. Windows 10 64-bit Professional
B. Microsoft Hardware-Assisted Virtualization Detection Tool
C. VirtualBox
D. Kitematic
E. BIOS-enabled virtualization
Answer: A,E
Explanation:
C: Make sure your Windows system supports Hardware Virtualization Technology and that virtualization is enabled.
Ensure that hardware virtualization support is turned on in the BIOS settings. For example:
E: To run Docker, your machine must have a 64-bit operating system running Windows 7 or higher.
References:
https://docs.docker.com/toolbox/toolbox_install_windows/
https://blogs.technet.microsoft.com/canitpro/2015/09/08/step-by-step-enabling-hyper-v-for-use-on-windows-10/
NEW QUESTION: 3
What is the name of the core-to-core transport mechanism used in Intel XEON processors?
A. Hyper Transport
B. Quick Path Interconnect
C. Northbridge
D. Crossbar switch
Answer: B
Explanation:
The way I understand it, Crossbar is not a technology name, but a switch that assist in communication between processors, memory etc, allowing inter core & inter CPU communication. QPI, FSB & HT are all types of connections, connected to crossbar switches. All the answers are connected to crossbards, but only Intel has QPI. I would still go with QPI www.site.uottawa.ca/~mbolic/ceg4131/Report Crossbar switches.pdf
A. Intel Xeon 7500 architecture The Intel Xeon 7500 series processor architectures uses an 8 port crossbar switch which implements the Intel QuickPath Interconnect (QPI) and routing layers. The Intel QPI is point-point interconnection link developed by Intel [1] to compete with HyperTransport. Prior to using QPI the Intel architecture was using the Front Side Bus (FSB) [2] which was the bus that carried data between CPU and the memory controller(northbridge) and I/O controller(southbridge).
The off-chip single memory controller often was the bottleneck which prevented faster CPUs from improving the overall performance of the system. Now, with crossbar implementation the microprocessor were able to integrate the northbridge on-chip for faster access As well: (Thanx MaaShar from Belgium)
http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technologygeneral.html
Intel@ QuickPath Technology uses Intel@ QuickPath Interconnect, which provides high-speed, point-to-point links inside and outside of the processor. In contrast to parallel buses, these links speed up data transfers by connecting distributed shared memory, the internal cores, the I/O hub, and other Intel@ processors.
NEW QUESTION: 4
Which statement is correct about Cisco Catalyst 6500 E-Series Switches?
A. All their FRUs are compatible with older Catalyst 6500 chassis.
B. They do not support CEF720 line cards.
C. They require different Cisco IOS code trains than older Catalyst 6500 chassis.
D. They support all existing supervisors, line cards, switch fabrics, and software releases.
Answer: D
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