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NEW QUESTION: 1
Which of the following are the common elements of platform as a service and software as a service? (Select two.)
A. Both allow the OS to be patched by the customer.
B. Both take advantage of the incremental scalability.
C. Both provide granular access to the backend storage.
D. Both implement hardware abstraction.
E. Both require the customer to maintain the hardware.
Answer: B,C

NEW QUESTION: 2
HOTSPOT
Match each technology to its description.


Answer:
Explanation:

Explanation:

http://h71000.www7.hp.com/doc/83final/b9073_90111/apas13.html The LPMC monitor, within the Support Tools Manager (STM) diagnostics, generates Information events for all cache errors that are detected. After three errors (Threshold) have been detected on a processor in 1440 minutes, or a 24-hour period of time (Period), the monitor deactivates that particular processor, marks it for deconfiguration on the next system reboot, and generates a SERIOUS event. After the failed processor is deactivated, the LPMC monitor attempts to activate one of the inactive Instant Capacity processors, if any are available. This method ensures the processing power of the system is unchanged.
A default value of "three" is assigned to Threshold, except for the PCX-W+ family of processors, which has a value of "five" assigned. The default value assigned to a Period is 1440 minutes, or 24 hours, in all possible processor configurations.
An inactive processor under warranty or support automatically replaces a failed processor. HP also services and replaces any failed processor.
http://www.techrepublic.com/whitepapers/mca-error-recovery-hp-ux-feature-for-recovering-frommachinecheck-aborts/354967
HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure.
Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).
http://dl.acm.org/citation.cfm?id=1057740 Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Both combinational and sequential logic circuits are expected to be affected. Many different latch designs to prevent soft errors due to particle strikes on the latch nodes have been proposed. We review these designs and compare them based on their robustness and their power and performance overheads. We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch. We expect this work will help designers to select latches for applications where soft error is an important design metric.
http://en.wikipedia.org/wiki/Montecito_(processor)
Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology

NEW QUESTION: 3
Refer to the exhibit.

69 / 162
The safer , easier way to help you pass any IT exams.
Ephone 1 has three active calls. The first two calls were inbound calls, which the user put on hold to place a third call outbound. What will happen on ephone 1 when a fourth call arrives for extension 2001?
A. The fourth call will be delivered to ephone 1 because it can handle up to five calls on each button.
B. The fourth call will be held temporarily by the IOS Software until ephone 1 disconnects one of the active calls.
C. The fourth call will be delivered to ephone 1 because the huntstop channel setting is not yet saturated.
D. The fourth call will be delivered to ephone 1 because it only received two inbound calls, one call less than the busy-trigger-per-button setting.
E. The fourth call will not be delivered and the caller will hear a user busy tone.
Answer: E
Explanation:
Explanation/Reference:
Explanation:
Because on line maximum 4 calls can be placed when user put the call on hold is consume a channel and reach the maximum number of calls on line.